build: improve dependency file generation

Make.rules

@@ -172,7 +172,7 @@ if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ),                 \
 #####
 # Handle options to gcc.
 
-c_flags		= -Wp,-MD,$(depfile) $(CFLAGS_ALL) $(CFLAGS_$(notdir $@))
+c_flags		= -Wp,-MD,$(depfile),-MT,$@ $(CFLAGS_ALL) $(CFLAGS_$(notdir $@))
 ld_flags	= $(LDFLAGS_ALL) $(LDFLAGS_$(notdir $@))
 
 #####
@@ -183,8 +183,7 @@ cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
 
 define rule_cc_o_c
 	$(call echo-cmd,cc_o_c) $(cmd_cc_o_c);		\
-	(echo 'cmd_$@ := $(call make-cmd,cc_o_c)'; \
-	 echo -n "\n$(obj)/" ; cat $(depfile)) \
+	(echo 'cmd_$@ := $(call make-cmd,cc_o_c)'; echo; cat $(depfile)) \
 		> $(dot-target).cmd ; \
 	rm $(depfile)
 endef