testing/py3-litex: new aport

https://github.com/enjoy-digital/litex
infrastructure to create FPGA Cores/SoCs and full FPGA based systems

testing/py3-litex/0001-litedram-phy-lpddr-fix-use-of-invalid-escape-sequenc.patch

+From 37e1f346e5a47dff74c0535c3b3cacd8f7b144dd Mon Sep 17 00:00:00 2001
+From: Marian Buschsieweke <marian.buschsieweke@posteo.net>
+Date: Thu, 11 Jan 2024 09:46:43 +0100
+Subject: [PATCH] litedram/phy/lpddr*: fix use of invalid escape sequence
+
+This fixes multiple instances of:
+
+litedram/phy/lpddr4/commands.py:209
+  litedram-2023.12/litedram/phy/lpddr4/commands.py:209: DeprecationWarning: invalid escape sequence '\d'
+    "BA(\d+)": lambda i: self.dfi.bank[i],
+---
+ litedram/phy/lpddr4/commands.py | 24 ++++++++++----------
+ litedram/phy/lpddr5/commands.py | 40 ++++++++++++++++-----------------
+ 2 files changed, 32 insertions(+), 32 deletions(-)
+
+diff --git a/litedram/phy/lpddr4/commands.py b/litedram/phy/lpddr4/commands.py
+index 737e318..90ade80 100644
+--- a/litedram-2023.12/litedram/phy/lpddr4/commands.py
++++ b/litedram-2023.12/litedram/phy/lpddr4/commands.py
+@@ -199,18 +199,18 @@ class Command(Module):
+         assert len(self.dfi.address) >= 17, "At least 17 DFI addressbits needed for row address"
+         mr_address = self.dfi.bank if is_mrw else self.dfi.address
+         rules = {
+-            "H":       lambda: 1,  # high
+-            "L":       lambda: 0,  # low
+-            "V":       lambda: 0,  # defined logic
+-            "X":       lambda: 0,  # don't care
+-            "BL":      lambda: 0,  # on-the-fly burst length, not using
+-            "AP":      lambda: self.dfi.address[10],  # auto precharge
+-            "AB":      lambda: self.dfi.address[10],  # all banks
+-            "BA(\d+)": lambda i: self.dfi.bank[i],
+-            "R(\d+)":  lambda i: self.dfi.address[i],  # row
+-            "C(\d+)":  lambda i: self.dfi.address[i],  # column
+-            "MA(\d+)": lambda i: mr_address[i],  # mode register address
+-            "OP(\d+)": lambda i: self.dfi.address[i],  # mode register value, or operand for MPC
++            "H":        lambda: 1,  # high
++            "L":        lambda: 0,  # low
++            "V":        lambda: 0,  # defined logic
++            "X":        lambda: 0,  # don't care
++            "BL":       lambda: 0,  # on-the-fly burst length, not using
++            "AP":       lambda: self.dfi.address[10],  # auto precharge
++            "AB":       lambda: self.dfi.address[10],  # all banks
++            "BA(\\d+)": lambda i: self.dfi.bank[i],
++            "R(\\d+)":  lambda i: self.dfi.address[i],  # row
++            "C(\\d+)":  lambda i: self.dfi.address[i],  # column
++            "MA(\\d+)": lambda i: mr_address[i],  # mode register address
++            "OP(\\d+)": lambda i: self.dfi.address[i],  # mode register value, or operand for MPC
+         }
+         for pattern, value in rules.items():
+             m = re.match(pattern, bit)
+diff --git a/litedram/phy/lpddr5/commands.py b/litedram/phy/lpddr5/commands.py
+index 9fd13ee..52733ec 100644
+--- a/litedram-2023.12/litedram/phy/lpddr5/commands.py
++++ b/litedram-2023.12/litedram/phy/lpddr5/commands.py
+@@ -275,27 +275,27 @@ class Command(Module):
+         op = mpc_op if is_mpc else self.dfi.address
+ 
+         rules = {
+-            "H":       lambda: 1,  # high
+-            "L":       lambda: 0,  # low
+-            "V":       lambda: 0,  # defined logic
+-            "X":       lambda: 0,  # don't care
+-            "AB":      lambda: self.dfi.address[10],  # all banks
+-            "AP":      lambda: self.dfi.address[10],  # auto precharge
+-            "RFM":     lambda: 0,  # TODO: 1=RFM, 0=REF (Refresh Managemenent, only if r/o MR[27][0]=1, else always REF)
+-            "SB(\d+)": lambda i: 0,  # sub-bank selection related to RFM
+-            "WS_WR":   lambda: self.wck_sync == WCKSyncType.WR,  # Write WCK2CK SYNC
+-            "WS_RD":   lambda: self.wck_sync == WCKSyncType.RD,  # Read WCK2CK SYNC
+-            "WS_FS":   lambda: self.wck_sync == WCKSyncType.FS,  # FAST SYNC
+-            "DC(\d+)": lambda i: 0,  # Data Copy, unimplemented
+-            "WRX":     lambda: 0,  # Write X function, unimplemented
+-            "WXSA":    lambda: 0,  # Write X function, unimplemented
+-            "WXSB":    lambda: 0,  # Write X function, unimplemented
+-            "BA(\d+)": lambda i: self.dfi.bank[i],  # only BA0-2 is used, in BG/B16 modes we always refresh banks (x, x+8)
+-            "R(\d+)":  lambda i: self.dfi.address[i],  # row
++            "H":        lambda: 1,  # high
++            "L":        lambda: 0,  # low
++            "V":        lambda: 0,  # defined logic
++            "X":        lambda: 0,  # don't care
++            "AB":       lambda: self.dfi.address[10],  # all banks
++            "AP":       lambda: self.dfi.address[10],  # auto precharge
++            "RFM":      lambda: 0,  # TODO: 1=RFM, 0=REF (Refresh Managemenent, only if r/o MR[27][0]=1, else always REF)
++            "SB(\\d+)": lambda i: 0,  # sub-bank selection related to RFM
++            "WS_WR":    lambda: self.wck_sync == WCKSyncType.WR,  # Write WCK2CK SYNC
++            "WS_RD":    lambda: self.wck_sync == WCKSyncType.RD,  # Read WCK2CK SYNC
++            "WS_FS":    lambda: self.wck_sync == WCKSyncType.FS,  # FAST SYNC
++            "DC(\\d+)": lambda i: 0,  # Data Copy, unimplemented
++            "WRX":      lambda: 0,  # Write X function, unimplemented
++            "WXSA":     lambda: 0,  # Write X function, unimplemented
++            "WXSB":     lambda: 0,  # Write X function, unimplemented
++            "BA(\\d+)": lambda i: self.dfi.bank[i],  # only BA0-2 is used, in BG/B16 modes we always refresh banks (x, x+8)
++            "R(\\d+)":  lambda i: self.dfi.address[i],  # row
+             # LPDDR5 specs split the regular column address into C[5:0] "column address" and B[3:0] "burst address"
+-            "C(\d+)":  lambda i: self.dfi.address[i + 4],
+-            "MA(\d+)": lambda i: mr_address[i],  # mode register address
+-            "OP(\d+)": lambda i: op[i], # mode register value, or operand for MPC
++            "C(\\d+)":  lambda i: self.dfi.address[i + 4],
++            "MA(\\d+)": lambda i: mr_address[i],  # mode register address
++            "OP(\\d+)": lambda i: op[i], # mode register value, or operand for MPC
+         }
+ 
+         for pattern, value in rules.items():
+-- 
+2.43.0
+

testing/py3-litex/0002-litex-fix-invalid-escape-sequence.patch

+This fixes:
+
+    test/test_cpu.py:15
+      /home/maribu/Repos/software/aports/testing/py3-litex/src/litex-2023.12/test/test_cpu.py:15: DeprecationWarning: invalid escape sequence '\['
+        litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>']
+--- a/litex-2023.12/test/test_cpu.py	2024-01-11 15:12:24.107360027 +0100
++++ b/litex-2023.12/test/test_cpu.py	2024-01-11 15:13:21.403348076 +0100
+@@ -12,7 +12,7 @@ import os
+ class TestCPU(unittest.TestCase):
+     def boot_test(self, cpu_type, jobs, cpu_variant="standard"):
+         cmd = f'litex_sim --cpu-type={cpu_type} --cpu-variant={cpu_variant} --opt-level=O0 --jobs {jobs}'
+-        litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>']
++        litex_prompt = [b'\033\\[[0-9;]+mlitex\033\\[[0-9;]+m>']
+         is_success = True
+         with open("/tmp/test_boot_log", "wb") as result_file:
+             p = pexpect.spawn(cmd, timeout=None, logfile=result_file)

testing/py3-litex/APKBUILD

+# Contributor: Marian Buschsieweke <marian.buschsieweke@posteo.net>
+# Maintainer: Marian Buschsieweke <marian.buschsieweke@posteo.net>
+pkgname=py3-litex
+_pkgname=litex
+pkgver=2023.12
+pkgrel=0
+pkgdesc="infrastructure to create FPGA Cores/SoCs and full FPGA based systems"
+url="https://github.com/enjoy-digital/litex"
+license="BSD-2-Clause"
+# ppc64le: verilator verilator-dev
+# s390x: verilator verilator-dev, picolibc-riscv-none-elf
+# armv7: verilator verilator-dev, picolibc-riscv-none-elf
+# armhf: verilator verilator-dev, picolibc-riscv-none-elf
+# riscv64: verilator verilator-dev, picolibc-riscv-none-elf
+# aarch64: verilator verilator-dev
+# x86: unit test failures
+arch="all !ppc64le !s390x !armv7 !armhf !riscv64 !aarch64 !x86"
+depends="
+	py3-migen
+	py3-packaging
+	py3-pyserial
+	py3-requests
+	py3-yaml
+	python3
+	"
+makedepends="
+	py3-setuptools
+	py3-gpep517
+	py3-wheel
+	py3-installer
+	"
+checkdepends="
+	bash
+	json-c-dev
+	libevent-dev
+	linux-headers
+	meson
+	picolibc-riscv-none-elf
+	py3-litex-hub-modules
+	py3-pexpect
+	py3-pytest
+	verilator
+	verilator-dev
+	zlib-dev
+	"
+source="
+	$pkgname-$pkgver.tar.gz::https://github.com/enjoy-digital/litex/archive/refs/tags/$pkgver.tar.gz
+	litescope-$pkgver.tar.gz::https://github.com/enjoy-digital/litescope/archive/refs/tags/$pkgver.tar.gz
+	litex-boards-$pkgver.tar.gz::https://github.com/litex-hub/litex-boards/archive/refs/tags/$pkgver.tar.gz
+
+	0001-litedram-phy-lpddr-fix-use-of-invalid-escape-sequenc.patch
+	0002-litex-fix-invalid-escape-sequence.patch
+	"
+builddir="$srcdir"
+subpackages="
+	$pkgname-pyc
+	$pkgname-full
+	py3-litescope
+	py3-litex-boards
+	"
+
+_cores_enjoy_digital="
+	dram:DRAM
+	eth:Ethernet
+	iclink:Inter-Chip-Communication
+	jesd204b:JESD204B
+	pcie:PCIe
+	sata:SATA
+	sdcard:SDCard
+	"
+_cores_litex_hub="
+	spi:SPI
+	"
+_cores="$_cores_enjoy_digital $_cores_litex_hub"
+
+for _core_name in $_cores_enjoy_digital; do
+	_core=$(echo "$_core_name" | cut -d : -f 1)
+	subpackages="$subpackages py3-lite$_core:_subpkg_core"
+	source="$source py3-lite$_core-$pkgver.tar.gz::https://github.com/enjoy-digital/lite$_core/archive/refs/tags/$pkgver.tar.gz"
+done
+
+for _core_name in $_cores_litex_hub; do
+	_core=$(echo "$_core_name" | cut -d : -f 1)
+	subpackages="$subpackages py3-lite$_core:_subpkg_core"
+	source="$source py3-lite$_core-$pkgver.tar.gz::https://github.com/litex-hub/lite$_core/archive/refs/tags/$pkgver.tar.gz"
+done
+
+prepare() {
+	default_prepare
+
+	# remove and rebuild x86_64 glibc binaries used in litesata test
+	cd "$srcdir/litesata-$pkgver/test/model"
+	rm crc scrambler
+	gcc -Os -o scrambler scrambler.c
+	gcc -Os -o crc crc.c
+}
+
+build() {
+	echo "--> Building LiteX"
+	cd "$srcdir/litex-$pkgver"
+	gpep517 build-wheel \
+		--wheel-dir dist \
+		--output-fd 3 3>&1 >&2
+
+	echo "--> Building LiteX-Boards"
+	cd "$srcdir/litex-boards-$pkgver"
+	gpep517 build-wheel \
+		--wheel-dir dist \
+		--output-fd 3 3>&1 >&2
+
+	echo "--> Building LiteScope"
+	cd "$srcdir/litescope-$pkgver"
+	gpep517 build-wheel \
+		--wheel-dir dist \
+		--output-fd 3 3>&1 >&2
+
+	for _core_name in $_cores; do
+		_core=$(echo "$_core_name" | cut -d : -f 1)
+		_name=$(echo "$_core_name" | cut -d : -f 2)
+		echo "--> Building LiteX core $_name"
+
+		cd "$srcdir/lite$_core-$pkgver"
+		gpep517 build-wheel \
+			--wheel-dir dist \
+			--output-fd 3 3>&1 >&2
+	done
+}
+
+check() {
+	cd "$srcdir/litex-$pkgver"
+	python3 -m venv --clear --without-pip --system-site-packages "$srcdir"/testenv
+	"$srcdir"/testenv/bin/python3 -m installer dist/*.whl
+	"$srcdir"/testenv/bin/python3 -m installer "$srcdir/litex-boards-$pkgver"/dist/*.whl
+	"$srcdir"/testenv/bin/python3 -m installer "$srcdir/litescope-$pkgver"/dist/*.whl
+
+	for _core_name in $_cores; do
+		_core=$(echo "$_core_name" | cut -d : -f 1)
+		"$srcdir"/testenv/bin/python3 -m installer "$srcdir/lite$_core-$pkgver"/dist/*.whl
+	done
+
+	echo "--> Testing LiteX"
+	# CPU test fails with "%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt"
+	env PATH="$srcdir/testenv/bin:$PATH" "$srcdir"/testenv/bin/python3 -m pytest -v \
+		--deselect test/test_cpu.py::TestCPU::test_cpu
+
+	for _core_name in $_cores; do
+		_core=$(echo "$_core_name" | cut -d : -f 1)
+		_name=$(echo "$_core_name" | cut -d : -f 2)
+		echo "--> Testing LiteX core $_name"
+		cd "$srcdir/lite$_core-$pkgver"
+
+		env PATH="$srcdir/testenv/bin:$PATH" "$srcdir/testenv/bin/python3" -m pytest -v
+
+	done
+}
+
+package() {
+	python3 -m installer -d "$pkgdir" \
+		"$srcdir/litex-$pkgver"/dist/*.whl
+
+	for _core_name in $_cores; do
+		_core=$(echo "$_core_name" | cut -d : -f 1)
+		python3 -m installer -d "$pkgdir" \
+			"$srcdir/lite$_core-$pkgver"/dist/*.whl
+	done
+
+	python3 -m installer -d "$pkgdir" \
+		"$srcdir/litescope-$pkgver"/dist/*.whl
+
+	python3 -m installer -d "$pkgdir" \
+		"$srcdir/litex-boards-$pkgver"/dist/*.whl
+}
+
+_subpkg_core() {
+	_core="${subpkgname#py3-lite}"
+	for _core_name in $_cores; do
+		if [ "$_core" = "$(echo "$_core_name" | cut -d : -f 1)" ]; then
+			_name=$(echo "$_core_name" | cut -d : -f 2)
+		fi
+	done
+	pkgdesc="Small footprint and configurable $_name core"
+	depends="$depends py3-litex"
+
+	amove usr/lib/python3*/site-packages/"lite$_core"
+	amove usr/lib/python3*/site-packages/"lite$_core"-*.dist-info
+}
+
+litescope() {
+	pkgdesc="Small footprint and configurable embedded FPGA logic analyzer"
+	depends="$depends py3-litex"
+	amove usr/lib/python3*/site-packages/litescope
+	amove usr/lib/python3*/site-packages/litescope-*.dist-info
+}
+
+boards() {
+	pkgdesc="LiteX boards files"
+	depends="$depends py3-litex"
+	amove usr/lib/python3*/site-packages/litex_boards
+	amove usr/lib/python3*/site-packages/litex_boards-*.dist-info
+}
+
+full() {
+	pkgdesc="Meta package to install full LiteX framework"
+	depends="
+		bash
+		json-c-dev
+		libevent-dev
+		linux-headers
+		meson
+		picolibc-riscv-none-elf
+		py3-litescope
+		py3-litex
+		py3-litex-boards
+		py3-litex-hub-modules
+		verilator
+		verilator-dev
+		zlib-dev
+		"
+	for _core_name in $_cores; do
+		_core=$(echo "$_core_name" | cut -d : -f 1)
+		depends="$depends py3-lite$_core"
+	done
+
+	mkdir -p "$subpkgdir"
+}
+
+sha512sums="
+6fa3888d6f80214ef8a2e1af439ac652794deba8a0da97cc7d7bc0f6fd5e45898966be22c117629d91e8df6ad7dbd383d7a3ae50567f0eeb7f1cc98d36b31e08  py3-litex-2023.12.tar.gz
+4aaa452fc6dbb2edbc9c61c7a9c66d70763dd2a6a3b12eac1a9185b117f31e94d6d532462971cb2082002dc8f4d95c6f4bb1f07d6e692fa967ebdfa3aaf1a1d3  litescope-2023.12.tar.gz
+f41ac30e1b76bc06341827c1600c1e072ce457c03b9170fe34d4d1c5b9c2e7c8851615139b9d0f4107b33aee26bb20b3918ec8111115b35b0d451757e11234b4  litex-boards-2023.12.tar.gz
+b975f8d3e38f4b64e775dd026e173002007f789d9ec959442b3ed9fc00d37ba3a4891af15c219e806deda272edda37e05aa4a241e7db0fe8c36297dafa55b64e  0001-litedram-phy-lpddr-fix-use-of-invalid-escape-sequenc.patch
+faae763691fa50db3f9358b5abd64e23bc2e8974b125b2df82c58aca778900253bbab20673412c57174bf7767368fa1e706fde5b54c281ff212d821859e6a076  0002-litex-fix-invalid-escape-sequence.patch
+5137b7db6db5c33223c0cf0c51dd3eb724f83a7050dfba8e68d4aeb9514095ac1afd0105645a9381b2f68751d17e95276ffe464cf01e1fa44e078a7092e2ea07  py3-litedram-2023.12.tar.gz
+454b51651ffe863f6f81b8a010805550c197845f719ad5d7e67454c4ce9a42b290adb92c9aab355dbdbc53484bf436baf2a9d5921c3d7053ac6cbe0ce8c56161  py3-liteeth-2023.12.tar.gz
+fc019f3def7790aa9822762c63d5578555af30a731da56976e7ec1b91591d833dadca91f9cc4ffd3a457ad76484b13a0e4f67b9f66a90d78b6f3106b34617720  py3-liteiclink-2023.12.tar.gz
+f6e4bf357e24b898e08079a119912ff58b48e754544313611914dba1e13dd921e5ee919a5559c4b8f77c9768203b396fbc49ac5019a488a797ebcedc24754409  py3-litejesd204b-2023.12.tar.gz
+8155a87e320345741b4a7f187651c15a704d65ed0c4e95fe5994c913632b20ae56ab8f36968a606658e361c9a8968447e31b3c00ff34f2bd66bd89dc2001c09f  py3-litepcie-2023.12.tar.gz
+ab62eb5c183e4559ea352c561b4c9b985ffc917c686f6dac121ec64558a873a5225e591c44daf473cbb56fab719703e89bbcd8710ae94b9e5522f7500a495ee1  py3-litesata-2023.12.tar.gz
+755f253a0c0e720c16970f515c1b4aa82f3f4401f9cf2301803a514942cf1b4211c43aa602910beb7181bb53f435cb9c41cb96d54423e110e3914f4512b559c1  py3-litesdcard-2023.12.tar.gz
+19946e9e4a8f8085f5644e8b51fb588332598fdede7e5f9acb30160a794fa8768f4b9a4ba0cc4532e995debbe3059e32f72029722ce9624ee3531bd65543e58b  py3-litespi-2023.12.tar.gz
+"